FIG. 1B illustrates in simplified form a cross section of a pair of partially completed DRAM cells formed in substrate 10 and having a P-well 15. A trench has been etched into the substrate and capacitor 100 has been formed in the lower portion, with buried plate 107, dielectric layer 106, and center electrode 110.
In the upper portion of the trench, a vertical transistor 200 has been formed, with buried strap 127 as the lower electrode, gate 140 and upper electrode behind the plane of the paper.
Lower collar 122 and isolating dielectric are conventional. Pad oxide 20 and pad nitride 25 will be replaced by the array top oxide and wordlines and bitlines will be added later.
In the course of etching a deep trench in a silicon substrate, a conventional configuration of orienting the trench in a (100) wafer is the <100> configuration, in which the long axes of the oval trenches are printed at the wafer surface parallel to a <100> crystallographic direction of the substrate (diagramed in FIG. 1A). In this configuration, the formed trench assumes a square shape in the bottom, as shown in FIG. 2A with dashed line 102 as the initial trench boundary and solid line 104 as the boundary after bottle etch; an oval shape at the wafer surface, as shown in FIG. 2C; and an octagon shape 220 in the upper portion of the trench, as shown in FIG. 2B. The change of trench shape at different depth is due to the fact that etch rates are different at different crystallographic orientations. Specifically, the {100} surfaces of the silicon are etched at a greater rate than the {110} surfaces.
The <100> configuration has the advantage that the capacitance can be maximized by using the bottle etch step without having an excessive risk of trench merging because the differential etching along the crystal planes produces a square cross section that packs together tightly, even after the step of bottle etching. However, the octagonal cross section of the upper trench where the vertical capacitor is formed matches poorly with the stripe 210 that defines the active area (AA) by defining the isolation structures that separate devices and structures on the wafer surface.
FIG. 2B shows AA strips 210 that meet the octagons 220 that represent the trench cross section such that the corners of the octagons are at the trench-AA intersection. This results in the undesired variation of vertical transistor characteristics such as threshold voltage (Vt) when the trench-AA intersection is located slightly away from the corner or at the corner of the octagon.
Thus, the requirement of getting the highest capacitance in the trench and avoiding shorts between capacitors conflicts with the need for a tight alignment tolerance between the trench and the AA level.
FIG. 3B shows a cross section similar to FIG. 1B for an alternative version of a cell. FIG. 3A illustrates a difference in the crystal orientation of this version. The long axis of the trench is parallel to the <110> crystal axis. The results of this different crystal orientation are shown in FIG. 4, in which FIG. 4C shows the same printing on the top surface as FIG. 2C. FIG. 4B shows that the etching process produces an elongated octagon in the top portion of the trench where the vertical transistor is located. This has the beneficial effect of alleviating the alignment problem characteristic of the previous version because the AA stripe 210 is less likely to overlap corners of the elongated octagons 220′.
FIG. 4A illustrates a drawback of this version of the cell. The crystal orientation produces rectangular cross sections in the lower portion of the trenches. Trenches with such a shape have a tendency to merge with one another, so that it is necessary to increase the spacing between cells to avoid merging. Dashed lines 102′ show the trench boundary before bottle etch and solid lines 104′ show the boundary after bottle etch.
Scaling trench DRAM cell devices to sub-100 nm generations faces several challenges. First, the trench capacitance has to be maintained at a certain value (e.g. above 30 fF/cell) so that the device can function properly. Unfortunately, as the trench size is scaled down, the trench depth is also decreased. This directly translates to a decrease of capacitance. Capacitance enhancement after deep trench etch has to be implemented for sub-100 nm trench memory devices.
The second challenge is the tight overlay tolerance. Misalignments could lead to the degradation or even failure of the device. Techniques have been developed for each individual issue, but integration of these techniques to solve all these issues at the same time is extremely difficult. The difficulty is due to the fact that the preferred trench orientation with respect to silicon substrates for some techniques is undesired for other techniques.
For example, widening the trench by wet etching silicon to form a bottle in the capacitance region is one of the most straightforward techniques for trench capacitance enhancement. The <100> configuration in which trench axes are parallel to the <100> directions of the silicon substrate, is desired for a maximal capacitance enhancement. However, this configuration results in a minimal tolerance for the AA (active area) to DT (deep trench) overlay.
On the other hand, the AA-DT overlay tolerance becomes maximal for the <110> configuration in which the trench axes are parallel to the <110> direction of the silicon substrate, but this configuration suffers from trench merging when a bottling process is implemented.
The art could benefit from a trench capacitor-vertical transistor process that preserves tight tolerance between the trench and the active area.